IEEE AICAS: AI Hardware Conference | Generated by AI
Question: What is IEEE AICAS?
Answer: It’s the flagship conference of the IEEE Circuits and Systems Society for AI hardware — the intersection of AI algorithms and the circuits/systems that run them, from edge chips to datacenter accelerators. Established to promote research at the frontiers of artificial intelligence circuits and systems, addressing the new computing paradigms needed for AI workloads running on everything from edge devices to cloud servers.
Not a pure ML conference (not NeurIPS/ICML) — it’s CAS people (circuit designers, chip architects, VLSI) plus AI researchers meeting in the middle. Think: quantized/low-power NN inference accelerators, in-memory computing, neuromorphic chips, spiking neural nets, edge AI silicon.
Current state:
- AICAS 2025 was held in Bordeaux, France (April 28-30, 2025), following prior years in Hangzhou, Incheon, Washington DC, Genova, and Hsinchu.
- The 8th edition, AICAS 2026, runs September 16-18, 2026, organized by IEEE CASS with the IEEE CAS Vietnam and China Chapters, held in Ha Long Bay, Vietnam.
- Papers go up to 5 pages (4 technical + 1 references-only), submitted anonymously; best papers get recommended to IEEE TCAS-AI or IEEE TVLSI. Proceedings go to IEEE Xplore.
- AICAS 2024 (Abu Dhabi) even ran a Grand Challenge on software/hardware co-optimization for LLM inference on CPU — relevant to what you’re doing with GPU clusters, just flipped to the hardware-design side.
If you’re evaluating it as a publication venue: it’s more niche/hardware-focused than a place to publish “we fine-tuned a 760M model” work — better fit would be if you have something on inference acceleration, quantization for edge deployment, or custom silicon/kernel work.
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