Computer Organization - Exam Questions

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April 2022 National Higher Education Self-Study Examination

Computer Organization

(Course Code 02318)

Instructions:

  1. The exam paper consists of two parts: Part 1 (Multiple Choice) and Part 2 (Non-Multiple Choice).
  2. Candidates must answer the questions in the designated locations on the answer sheet (paper) in the order of the questions. Answers written on the exam paper will be invalid.
  3. The filling and drawing sections must use a 2B pencil, and the writing section must use a black ink pen.

Part 1: Multiple Choice Questions

I. Multiple Choice Questions: This section consists of 10 questions, 1 point each, for a total of 10 points.

  1. Which of the following options represents the speed of floating-point operations of a computer?
    • A. CPI
    • B. MIPS
    • C. MFLOPS
    • D. Clock Frequency
  2. In the IEEE754 single-precision (32-bit) floating-point representation format, the bias constant of the exponent represented by the biased code is
    • A. 127
    • B. 128
    • C. 255
    • D. 256
  3. In a computer, the alignment operation for floating-point addition and subtraction is
    • A. The number with the smaller exponent increases its exponent and shifts the mantissa to the right.
    • B. The number with the smaller exponent increases its exponent and shifts the mantissa to the left.
    • C. The number with the larger exponent decreases its exponent and shifts the mantissa to the left.
    • D. The number with the larger exponent decreases its exponent and shifts the mantissa to the right.
  4. The range of an 8-bit binary fixed-point number X in two’s complement representation is
    • A. $-128<X<128$
    • B. $-128<X \leqslant 128$
    • C. $-128 \leqslant X \leqslant 127$
    • D. $-128 \leqslant X \leqslant 128$
  5. When two n-bit two’s complement numbers are added, $\mathrm{C}{n}$ and $\mathrm{C}{n-1}$ are the carry bits generated by the highest and next highest bits, respectively. The logical expression for overflow generation is
    • A. $\mathrm{OF}=\mathrm{C}_{n}$
    • B. $\mathrm{OF}=\mathrm{C}{n}+\mathrm{C}{n-1}$
    • C. $\mathrm{OF}=\mathrm{C}{n} \oplus \mathrm{C}{n-1}$
    • D. $\mathrm{OF}=\mathrm{C}{n}-\mathrm{C}{n-1}$
  6. The instruction provides a register number and a constant. If the operand address is equal to the sum of the register content and the constant, then the addressing mode of the operand is
    • A. Direct Addressing
    • B. Register Addressing
    • C. Displacement Addressing
    • D. Indirect Addressing
  7. Which of the following descriptions best fits a RISC computer?
    • A. Rich instruction addressing modes, most instructions can access memory.
    • B. Only a few instructions can access memory.
    • C. The instruction set has a large number of instructions.
    • D. The instruction set has instructions of variable lengths.
  8. In a computer using a microprogram controller, the microprogram is stored in
    • A. Stack
    • B. Main Memory
    • C. CPU
    • D. Disk
  9. Cache memory generally uses
    • A. Dynamic Memory
    • B. Static Memory
    • C. Read-Only Memory
    • D. Non-Volatile Memory
  10. Saving the breakpoint during the interrupt response process refers to
    • A. Pushing the contents of each general-purpose register in the CPU onto the stack.
    • B. Pushing the content of the program counter PC onto the stack.
    • C. Pushing the content of the instruction register in the CPU onto the stack.
    • D. Pushing the content of the register SP onto the stack.

Part 2: Non-Multiple Choice Questions

II. Fill-in-the-Blanks: This section consists of 15 blanks, 1 point per blank, for a total of 15 points.

  1. In the development process of electronic digital computers, each era has its representative electronic devices. The first generation used vacuum tubes, the second generation used __, and from the third generation onwards, the main device is __.

  2. The addressing methods of the host to peripheral ports are divided into ___ and ___.

  3. The address mapping methods between main memory and Cache include __, fully associative mapping, and __ methods.

  4. Common input/output transmission control methods include direct program transmission, __, and __.

  5. The instruction formats in the MIPS instruction system are divided into ___ type, ___ type, and I type.

  6. When the IEEE754 single-precision floating-point number is represented in binary, the length of the exponent is ___ bits, and the length of the mantissa is ___ bits.

  7. Intel divides external interrupts into ___ interrupts and ___ interrupts.

  8. The average access time of a disk storage device mainly includes seek time, ___ time, and data transfer time.

III. Definition of Terms: This section consists of 5 questions, 3 points each, for a total of 15 points.

  1. (Computer) Word Length
  2. Parity Check Code
  3. Register Indirect Addressing
  4. Program Status Word Register (PSW)
  5. Random Access Memory (RAM)

IV. Short Answer Questions: This section consists of 4 questions, 5 points each, for a total of 20 points.

  1. In modern computer systems, there are operating systems, application programs, computer hardware, language processing systems, instruction set architectures, and other hardware and software. Draw a schematic diagram of the hierarchical relationship between them.

  2. Briefly describe the method of using an adder to implement two’s complement subtraction in an arithmetic unit, and draw a schematic diagram of the implementation circuit (Note: Treat the adder as a whole component, and do not need to draw its internal specific implementation).

  3. Briefly describe the correspondence between machine instructions, microprograms, microinstructions, microcommands, and microoperations in a microprogram controller.

  4. What is dynamic memory refresh? What are the refresh cycle arrangement methods?

V. Calculation Questions: This section consists of 3 questions, 6 points each, for a total of 18 points.

  1. The machine number of an IEEE754 single-precision floating-point number is 41A50000H. Convert it to a decimal representation of a real number.

  2. Use 8-bit binary two’s complement to calculate “ -115 - ( -100 )”. Express the result in two’s complement, and indicate the final flag bits SF, CF, OF, and ZF respectively.

  3. A high-level language program is compiled by a compiler to generate an executable instruction sequence, which runs on a machine with a clock frequency of 1 GHz. The instruction types used in the target instruction sequence are A, B, C, and D. The CPI of the four types of instructions on the machine and the number of instructions of each type are shown in the table below.

Instruction Type A B C D
CPI of each type 1 2 3 4
Number of instructions of each type 4 5 2 3

What is the CPI of the program? What is the execution time in ns? Round the calculation result to one decimal place.

VI. Comprehensive Application Questions: This section consists of 2 questions, question 31 is worth 12 points, and question 32 is worth 10 points, for a total of 22 points.

  1. A computer has a word length of 16 bits and uses a 16-bit fixed-length instruction format. The partial data path structure is shown in Figure 31. Assume that the output of MAR is always enabled. For the instruction SUBR1,(R2), please answer the following two questions.

(1) How many clock cycles are required in the execution phase? (2) What is the function of each clock cycle? What valid control signals are needed?

Note: The function of this instruction is: R[R1] ← R[R1] - M[R[R2]]

  1. Assume that a 4-way set associative mapping method is used between main memory and Cache, the data block size is 512 bytes, the Cache data area capacity is 32 k bytes, and the main memory space size is 1 M bytes, addressed by byte. ask:

(1) Into which parts is the main memory address divided? Which address bits are in each part? (2) What is the total capacity of the Cache in bits? (Including valid bit V)

April 2022 National Higher Education Self-Study Examination Computer Organization Exam Questions Answers and Scoring Reference

(Course Code 02318)

I. Multiple Choice Questions: This section consists of 10 questions, 1 point each, for a total of 10 points.

  1. C
  2. A
  3. A
  4. C
  5. C
  6. C
  7. B
  8. C
  9. B
  10. B

II. Fill-in-the-Blanks: This section consists of 15 blanks, 1 point per blank, for a total of 15 points.

  1. Transistor, Integrated Circuit
  2. Separate Addressing for Peripherals, Unified Addressing for Peripherals
  3. Direct Mapping, Set Associative Mapping
  4. Interrupt Transmission Mode, DMA Transmission Mode
  5. R, I
  6. 8, 23
  7. Maskable, Non-Maskable
  8. Rotational Latency

III. Definition of Terms: This section consists of 5 questions, 3 points each, for a total of 15 points.

  1. Answer: Refers to the basic number of binary digits that a computer processes in one operation. Such as 16 bits, 32 bits, 64 bits.
  2. Answer: Add a parity bit to the valid data bits so that the number of “1”s in the total encoding is an odd number or an even number.
  3. Answer: The address code given in the instruction is a register number, and the register stores the effective address of the operand.
  4. Answer: Records the current program’s running status and indicates the program’s working mode.
  5. Answer: Accessing memory cells by address, the access time of each memory cell is a constant, independent of the address size.

IV. Short Answer Questions: This section consists of 4 questions, 5 points each, for a total of 20 points.

  1. Answer: The hierarchical structure diagram of these five parts is as follows:
Application Programs
Language Processing System
Operating System
Instruction Set Architecture
Computer Hardware

Grading instructions: 1 point for each part, the graphical representation can be arbitrary, as long as it can explain the hierarchical relationship between the parts, it is considered correct.

  1. Answer: According to the basic principle of two’s complement operation: $[\mathrm{A}-\mathrm{B}]{\text{补}}=[\mathrm{A}]{\text{补}}+$ logical NOT($[\mathrm{B}]_{\text{补}}$) (2 points) The logical NOT([-B] complement) is to invert [B] complement and add 1, and adding 1 is achieved by setting the lowest carry Cin of the adder to 1. (1 point)

  2. Answer: A machine instruction corresponds to a microprogram (2 points), a microprogram consists of multiple microinstructions (1 point), a microinstruction generally generates multiple microcommands (1 point), and a microcommand generally corresponds to a microoperation (1 point).

  3. Answer: Since dynamic memory relies on capacitors to store information, and the capacitor capacity is limited and there is leakage, it cannot store charge for a long time. In order to ensure that the stored information is not lost, it is necessary to periodically replenish the charge to the capacitor at a certain time interval, which is the refresh of dynamic memory. (2 points) Refresh cycle arrangement methods include centralized refresh (1 point), distributed refresh (1 point), and asynchronous refresh (1 point).

V. Calculation Questions: This section consists of 3 questions, 6 points each, for a total of 18 points.

  1. Solution: $41 \mathrm{~A} 50000 \mathrm{H}=01000001101001010000000000000000 \mathrm{~B}(1$ point $)$ According to the IEEE754 single-precision floating-point format: Sign $\mathrm{s}=0$, the real number is a positive number, the mantissa decimal part $\mathrm{f}=(0.0100101) 2 (1$ point $)$ Exponent $\mathrm{e}=(\mathrm{1} 0000011) 2=(\mathrm{131}) 10(1$ point $)$ , the restored exponent is $\mathrm{e}-127=131-127=4$ (1 point), so the floating-point number is: $(1.0100101) 2 \times 2^{4}=(10100.101) 2=20.625$ (2 points)

  2. Solution: $[-115]{0}=10001101 \mathrm{~B},[-100]{0}=10011100 \mathrm{~B}, \quad[100]{0}=01100100 \mathrm{~B}$ $[-115]{0}-[-100]{0}=[-115]{0}+[100]_{0}=10001101 \mathrm{~B}+01100100 \mathrm{~B}=11110001 \mathrm{~B}(3$ points $)$ $\mathrm{SF}=1$ (1 point), $\mathrm{CF}=1$ (1 point), $\mathrm{OF}=0$ (1 point)

  3. Solution: The program has a total of 14 instructions, and the number of clock cycles included is $4 \times 1+5 \times 2+2 \times 3+3 \times 4=32$

    CPI is $32 / 14=2.3$ (3 points) Execution time is $32 / 1 \mathrm{G}=32.0 \mathrm{~ns}$ (3 points)

VI. Comprehensive Application Questions: This section consists of 2 questions, question 31 is worth 12 points, and question 32 is worth 10 points, for a total of 22 points.

  1. Answer: (1) 4 or 5 clock cycles are required (2 points) (2) Control Signal Function R2out, MARin MAR ← (R2) MarmR MDR ← M(MAR) $(\begin{array}{ll}2 & 2\end{array})$ R1out, Yin Y ← (R1) MDRout,AND Z ← Y - (MDR) $(\begin{array}{ll}2 & 2\end{array})$ Zout, R1in R1 ← (Z) (2 points) Among them, the 2nd and 3rd lines can be completed in one clock cycle or each occupy one clock cycle.

  2. Answer: (1) Main memory space 1 M bytes $=2^{20}$ bytes, so the main memory address has 20 bits, Cache has $32 \mathrm{~kB} / 512 \mathrm{~B}=64$ lines, every 4 lines are in 1 group, there are $64 / 4=16$ groups, so the group number needs 4 bits to represent. The main memory address is divided into three parts: block address, group number and tag (2 points), the three parts are: Block address 9 bits: $\mathrm{A}{8} \sim \mathrm{A}{9} \quad(2$ points $)$ Cache group number 4 bits: $\mathrm{A}{12} \sim \mathrm{A}{9} \quad(2$ points $)$ Tag $20-9-4=7$ bits: $\mathrm{A}{19} \sim \mathrm{A}{13} \quad(2$ points $)$ (2) Total Cache capacity $=32 \mathrm{~KB}+(7+1) \times 64=32 \mathrm{~KB}+64 \mathrm{~B}=32832 \mathrm{~B}=262656$ bit (2 points)

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